1. Field of the Invention
This invention relates in general to analog-to-digital converters (ADCs) and more particularly to high-speed, high-resolution, monolithic integrated circuit ADCs.
2. Description of the Related Art
Prior art analog to digital converters (ADCs) requiring high conversion rates and low latency typically use a string of stacked comparators connected to progressive voltages in a resistive ladder in a configuration well known as a basic flash converter. Significant amounts of research funds in telecommunications technology are continually being invested in order to increase speed and resolution within a limited number of prior art ADC circuit architectures.
Basic flash converters operate at very high speeds, in large part because they produce a complete data conversion for each clock cycle. An n-bit flash converter, however, typically requires 2.sup.n comparators, which are connected to progressively increasing voltage steps on a resistive ladder. The outputs of the comparators may be routed to a circuit widely known as a "thermometer" binary digital coding circuit to produce an n-bit binary output. As its name implies, the main advantage of the flash converter is its speed. Furthermore, these devices require no input sample-and-hold.
On the other hand, flash converters suffer from several well-known limitations, which become more pronounced at resolutions beyond eight bits. As is pointed out above, the number of comparators increases exponentially with resolution expressed in binary bits. Consequently, 256 comparators are needed even for modest 8-bit resolution. Further limitations include differential phase errors from clock skew, very large circuit area, and significant charge blowback.
Recent work directed toward overcoming the limitations described above have focused on multiple-stage flash converters (also known as "pipelined" flash converters) that use fewer bits per stage and thus reduce blowback, clock skew and circuit area. In these multiple-stage devices, each stage includes an input sample-and-hold circuit. Each stage in the pipeline then uses its own, separate flash converter to assess the magnitude of the input, and it then and feeds the digital result to a digital-to-analog converter (DAC) in a feedback loop. The difference between the DAC result and the input sample-and-hold output is amplified and fed to the sample-and-hold input of the next stage. Once the next stage has sampled the amplifier output signal, the previous stage is free to receive the next input signal.
As an example of one problem associated with the pipelined arrangement, assume the amplifier in the pipelined flash converter has a moderate gain of 16. The input signal to the first stage must in any event be sampled and held while the first flash converter estimates its amplitude and while the estimated amplitude output of the feedback DAC is subtracted from the input signal. Note that if the input signal were not sampled and held, it could change in amplitude by an amount sufficient to render the first flash digital amplitude estimate invalid or to drive the first stage amplifier into saturation before the output error signal is even sampled by the second stage. Thus, it is possible to increase the accuracy of a second flash converter in a pipelined stage by preceding it with an amplifier, but this in turn generally necessitates a sample-and-hold circuit.
Pipelined flash converters are capable of high speeds, such as 100 MHZ. Their resolution, however, has typically been limited to around ten bits because of differential linearity errors caused when the first error signal is handed off to the second stage in the pipeline. Another problem has been the lack of high integral linearity in the first stage DAC, which controls the overall linearity of the converter. These converters are therefore usually used in medium-resolution applications, from ten to twelve bits, where the inherent latency of three to five successive conversions does affect the quality of the output data.
In order to overcome the differential linearity limitations in basic and pipelined flash converters, much work in increasing converter resolution has focused on using sample-and-hold circuits and recursive techniques that employ just one feedback DAC with high differential and integral linearity. In these devices, the input is always sampled and held, after which the error signal between the DAC and the input signal is used on multiple cycles to drive the DAC toward the input signal. The final result is the DAC digital input word.
In early recursive converters, a single high-gain comparator processed the error signal. In these devices, the comparator output was then used to perform a binary search for the unknown value of the input signal using a technique widely known as successive approximation. A successive approximation register (SAR) in a feedback path received the comparator output and controlled the feedback DAC to perform a binary search for the held input voltage. Such converters required a relatively long time to convert the unknown input signal to a digital value because several clock cycles were required for each data conversion. With a good feedback DAC, such converters were capable of 16-bit resolution, but at least one clock cycle was required for each bit of resolution. Furthermore, an input sample-and-hold circuit was required to preserve the input amplitude during the time required for the conversion. Additionally, droop in the sample-and-hold over the time required for the conversion led to differential linearity inaccuracies in the converter unless redundant successive approximation steps near the end of the conversion were provided.
A significant improvement in the basic successive approximation converter was made when the single comparator was replaced by a moderate-resolution flash converter and the high-gain amplifier was replaced with a moderate but controlled-gain amplifier. The signal corresponding to the error between the input signal and the feedback DAC could then be converted (after amplification) by the multi-bit flash converter and processed in the feedback path by an adder, whose output was latched and controlled the DAC. The output of the latch also formed the second input of the adder.
Although these improved successive approximation devices could produce more than one bit on each clock cycle, they still required an input sample-and-hold circuit.
Another drawback stemmed from the amplifier: In order to provide high accuracy in these converters, the gain of the amplifier had to be increased on progressive steps. The settling time of the amplifier on high-gain steps was long, however, and significantly slowed the converter.
Further work on multi-bit recursive converters has focused on improving the speed and accuracy of the DAC in the feedback path. The four or five clock cycles required for the analog-to-digital conversion, however, still limits the overall speed of the converter.
When converting analog signals, it is desirable to remove input signal energy, particularly noise, in the frequency range near the sampling frequency of the converter. If the converter sampling frequency can be greatly increased, for example, by quantizing the input every clock cycle, then the order and cost of the anti-aliasing filter required in the input signal amplifier chain can be greatly reduced.
Accordingly, converters known as "sigma-delta" converters later became popular, since they were able to sample the input on each clock cycle and thus greatly ease anti-aliasing. This proved especially beneficial in filter design for audio applications. Early sigma-delta converters used simple, one-bit DACs, which provided inherently high integral linearity without requiring precision in the feedback DAC layout design. In the sigma-delta converter, an error signal produced by the difference between the input voltage and the one-bit DAC is fed to one or more discrete-time switched-capacitor integrating amplifiers before application to the one-bit comparator. The number of integrating amplifiers generally increases with the order of the loop. The one-bit sigma-delta is at present the common choice for audio applications.
One drawback of the sigma-delta converter is that it requires a very high over-sampling ratio (ratio of sampling rate to Nyquist sampling rate) in order to achieve high resolution. Other drawbacks relate to the order of the converter loop. It is well known, for example, that the order of the signal processing feedback loop may be increased to increase the input signal bandwidth for the same converter resolution. The number of integrating amplifiers provided must be increased, however, in proportion to the order of the required loop filter. Other well-known limitations of the sigma-delta converter include spurious tones and an output noise spectral density that increases with frequency at a rate that is proportional to the order of the converter loop.
In addition, the one-bit comparator output in such a converter must be processed over several clock cycles by a digital decimation filter at the output. It is well known that this decimation filter can become quite complex because it must have an order at least one higher than the basic loop in order to remove the large amount of converter quantization noise in the frequency region above the input signal bandwidth. The reason for this increase in quantization noise is the inherent reduction of gain through an integrating amplifier with increasing frequency.
Furthermore, sigma-delta converters sample the input on each clock cycle, and they do not produce a full conversion or quantized output for every sample. Their input generally includes a switched capacitor sampling circuit coupled to a discrete-time integrator--if an input sampling circuit were not used, inaccuracies in the integrator output would arise as a result of any time jitter or glitch energy in the DAC output every time its output changed.
Much early work on sigma-delta converters concentrated on increasing speed beyond the audio signal frequency range by increasing the order of the converter. Because increasing the order of a sigma-delta converter increases the slope of the output noise spectrum, a higher order decimation filter was typically required to recover the output data. Additionally, many techniques were developed to cope with increased stability problems and tones in higher order loops.
Despite increasing the order of the loop, it is still difficult to construct a one-bit sigma-delta converter that can process signal frequencies with bandwidths two orders of magnitude higher than the audio range. Nonetheless, processing such signal frequencies is required to fulfill many of the tasks required for telecommunications data transmission over, for example, copper wire subscriber loops. In an effort to increase the sigma-delta ADC sampling frequency for high-resolution telecommunications applications, designers have replaced the single comparator in the sigma-delta converter with a multi-bit flash converter at the output of the integrating amplifier chain in order to obtain more bits per conversion step. The multi-bit flash output is, in these designs, usually connected to a multi-bit feedback DAC. Such multi-bit flash signal processing reduces the quantization noise of the converter, but it loses the ease of DAC construction offered by the one-bit converter. Additionally, the quantization noise of the converter still increases with frequency in proportion to the order of the converter.
One attempt to ease the difficulty of constructing highly linear DACs in multi-bit sigma-delta converters has concentrated on the implementation of several different multiple-unit capacitive charge redistribution and switching techniques. In these devices, the feedback DAC is usually implemented by switching identical precision capacitors to either a positive or negative reference voltage rather than by switching just one capacitor to a voltage output DAC. Several techniques exist to alternate the precision capacitors in such a way as to reduce detrimental integral linearity effects due to inaccuracies in any one capacitor. In some of these devices, for example, the feedback capacitors are alternated in a pseudo-random fashion to provide acceptable integral linearity.
The multi-bit flash comparator in such a sigma-delta converter has certain speed advantages because the quantization noise form the flash is reduced in proportion to the number of comparators used. The signal bandwidth may be then also be increased considerably over the one-bit case, while still retaining a high signal-to-quantization-noise ratio. Because multiple capacitors are used in these systems, however, large switching current pulses are required in order to fully charge and discharge the input capacitors used for input voltage-to-charge conversion. Furthermore, the multi-bit sigma-delta converter still requires an input sampler and a complex output decimation filter with an order at least one higher than the basic loop.
In many telecommunications applications, such as copper wire-based digital subscriber loops, the noise performance of the ADC is most important at the highest frequencies. In these applications, however, the line attenuates the transmitted signals at high frequencies far greater than at low frequencies. Moreover, the overall resolution of the ADC is not nearly as important as the ADC equivalent resolution or quantization noise spectral density at the highest signal frequencies, which is the very the frequency region where sigma-delta converters have the worst noise performance.
What is needed is therefore a high-resolution ADC system that retains the advantages of the basic flash converter such as sampling the input at clock rates as high as the clock rate itself and completing a conversion on each clock cycle. This is especially true in the area of high-speed data transmission over channels such as twisted pairs of copper wires. At the same time, the system should avoid the conventional need for a sampler or sample-and-hold circuit connected to the input signal, since it would then also be able to avoid the transient currents required in existing devices in order to drive such an input sampling circuit. The ADC should be able to produce a first digital result with a quantizing noise that does not increase significantly with frequency. This in turn would eliminate the requirement for a high-order decimation filter and make possible the use of a second- or third-order lowpass digital filter to produce a second digital result having increased resolution. This invention provides such an ADC system.